1. Field of the Invention
The present invention generally relates to a structure, a fabrication method and an operation method for a memory cell. More particularly, the present invention relates to a structure, a fabrication method and an operation method for a non-volatile memory cell.
2. Description of Related Art
Due to the advantages of multiple data writing, reading, erasing and the stored data are retained even after the power is disconnected, the non-volatile memory has been widely applied to personal computers and electronic equipments.
A conventional non-volatile memory includes a floating gate and a control gate, which are made from polysilicon. While performing the programming or the erasing process on the non-volatile memory, bias voltages are applied to the source region, the drain region and the control gate, respectively, to inject electrons into the floating gate, or to pull electrons out from the floating gate. Conventionally, the injection of charges for the non-volatile memory includes the channel hot-electron injection (CHEI) mode and the Fowler-Nordheim Tunneling mode. Further, the modes for the programming and the erasing processes vary according to the methods for charge injection and ejection.
FIG. 1 illustrates a schematic cross-sectional view showing the structure of a conventional non-volatile memory. This non-volatile memory includes an n-type substrate 100, a p-type deep well region 102, an n-type well region 104, gate stacked structures 106a and 106b, an n type source region 108a, an n-type drain region 108b, a p-type shallow doped region 109, a p-type pocket doped region 110 and a plug 112. Accordingly, the p-type deep well region 102 is located in the substrate 100, the n-type well region 104 is allocated in the p-type deep well region 102. The gate stacked structures 106a and 106b are formed with, sequentially from the substrate 100, the tunnelling layer 114, the floating gate 116, the gate dielectric layer 118, the control gate 120 and the mask layer 122. Further, spacers 124 are disposed on the sidewalls of the gate stacked structures 106a and 106b. The n-type source region 108a is disposed in the n-type well region 104 and the p-type shallow doped regions 109 between two stacked gate structures 106a and 106b. The p-type shallow doped region 109 is disposed in the n-type well region 104 and contiguous to the surface of the substrate. The p-type pocket doped region 110 is disposed at the periphery of the two stacked gate structures 106a and 106b, and is extended to the undersides of the stacked gate structures 106a and 106b contiguous to a neighbouring p-type shallow doped region 109. Furthermore, the n-type drain region 108b is disposed in p-type pocket doping region 110 at the periphery of the stacked gate structures 106a and 106b. The conducting plug 112 is disposed on the substrate 100 and penetrates through the n-type drain region 108b and a portion of the p-type pocket doped region 110.
However, while voltages are applied to the source region, the drain region and the control gate layer to perform the programming process on a memory cell of the previously mentioned non-volatile memory, such as, a memory cell constituted with the stacked gate structure 106a or 106b, the non-selected memory cells are affected by the applied voltages for the programming process. This is due to the fact that the control gate and the source region of the selected memory cell are connected to the control gate and the source region of a neighbouring cell through a shared word line and a shared source line. Consequently, the reliability of the memory devices is compromised.
Besides, while performing the above mentioned programming process for a non-volatile memory, the current leakage easily occurs due to the presence of the source region, and the short distance between the source region and control gate.